1. Technical Field
Various embodiments of the present invention relate to a semiconductor memory apparatuses and related methods. In particular, certain embodiments relate to a semiconductor memory apparatus including a duty cycle correction circuit and related method for correcting the duty cycle.
2. Related Art
A duty cycle correction circuit is extensively used to correct a duty of a clock generated in a delay locked loop of a semiconductor memory apparatus.
The delay locked loop receives an external clock signal, performs a delay locked operation with respect to the external clock signal to generate an internal clock signal, and generates a delay locked signal when a delay value for the internal clock signal is locked.
When the delay locked signal is activated, the duty cycle correction circuit receives the internal clock signal as an input clock signal, and performs a duty correction operation with respect to the input clock signal to generate a corrected clock signal.
Here, on the basis of a single cycle of a clock signal with a predetermined frequency, duty refers to a ratio of a time during which a clock signal is in a logic low state to a time during which the clock signal is in a logic high state. When the time during which the clock signal is in the logic low state is substantially same as the time during which the clock signal is in the logic high state, the duty is 50%.
In a conventional semiconductor memory apparatus, a delay locked loop and a duty cycle correction circuit can perform a delay locked operation and a duty correction operation with respect to a clock signal only when the semiconductor memory apparatus is initialized, in order to reduce current consumption in the delay locked operation and the duty correction operation during a read operation and a write operation.
After initialization, the conventional semiconductor memory apparatus may substantially maintain preset delay value and duty value without performing the delay locked operation and the duty correction operation. Thus, in the conventional semiconductor memory apparatus, the duty correction operation is started when the delay value of the delay locked loop is locked and repeated multiple times until the duty is corrected to be above a predetermined level. When the duty is corrected to be above the predetermined level, the set duty value is maintained and various duty correction operations are stopped.
However, if the duty correction operations are finished, it may not be possible to correct a distortion of a duty of a clock signal which is input after the duty correction operations are finished.
FIG. 1 is a block diagram of a related-art duty cycle correction circuit.
Referring to FIG. 1, the duty cycle correction circuit includes a correction execution unit 10, a duty detection unit 20, a duty determination unit 30, and a correction code generation unit 40.
The correction execution unit 10 corrects a duty of an input clock signal CLK_d based on a multi-bit correction code DCC_CODE<0:n> to generate a corrected clock signal CLK.
The duty detection unit 20 checks the duty of the corrected clock signal CLK to generate a detection voltage det, which is an analog voltage.
The duty determination unit 30 generates a determination signal con based on the detection voltage det.
For example, the duty determination unit 30 activates the determination signal con when the detection voltage det is larger than a predetermined voltage, and deactivates the determination signal con when the detection voltage det is smaller than the predetermined voltage. The fact that the detection voltage det is larger than the predetermined voltage represents that the duty of the clock signal CLK has been distorted so as not to reach a predetermined level (for example, 60%). Meanwhile, the fact that the detection voltage det is smaller than the predetermined voltage represents that the duty of the clock signal CLK exists within the predetermined level.
The correction code generation unit 40 generates the multi-bit correction code DCC_CODE<0:n> in response to a delay locked signal Lock state, the detection voltage det, and the determination signal con.
The delay locked signal Lock state is activated after the delay locked loop locks a delay value for the clock signal CLK.
When the delay locked signal Lock state and the determination signal con are activated, the correction code generation unit 40 starts an operation of generating the multi-bit correction code DCC_CODE<0:n> based on the detection voltage det, is which is an analog voltage. When the determination signal con is deactivated, the correction code generation unit 40 completes the operation of generating the multi-bit correction code DCC_CODE<0:n> based on the detection voltage.
As described above, the duty cycle correction circuit according to the conventional art is formed in a closed loop as illustrated in FIG. 1, thereby continuously correcting the duty of the clock signal CLK.